{"id":1584,"date":"2017-01-01T19:47:00","date_gmt":"2017-01-01T22:47:00","guid":{"rendered":"http:\/\/pc5.frbb.utn.edu.ar\/frbb\/?p=1584"},"modified":"2024-12-17T19:21:21","modified_gmt":"2024-12-17T22:21:21","slug":"4461tc","status":"publish","type":"post","link":"https:\/\/www.frbb.utn.edu.ar\/frbb\/scyt\/proyectos\/finalizados-con-incentivo\/4461tc\/","title":{"rendered":"4461TC M\u00e9todos Concurrentes para Arquitecturas Digitales en Dispositivos L\u00f3gicos Configurables (FPGA)"},"content":{"rendered":"\n
\n
\n

Grupo:<\/strong> SITIC
\n Director:<\/strong> Cayssials, Ricardo Lu\u00eds<\/p>\n

Fecha de Inicio<\/strong>: 01\/01\/2017 Fecha de Finalizaci\u00f3n<\/strong>: 31\/12\/2019<\/p>\n\t\t

En aplicaciones modernas de sistemas digitales, los requerimientos cada vez m\u00e1s exigentes impuestos por las aplicaciones y el mercado fuerzan el desarrollo de t\u00e9cnicas y metodolog\u00edas de dise\u00f1os flexibles, eficientes y con niveles elevados de abstracci\u00f3n para dominar las crecientes complejidades de las implementaciones. En este contexto, el dise\u00f1o concurrente (codise\u00f1o) de Hardware y Software (HW\/SW Co-Design) propone una alternativa para abordar las nuevas exigencias con una mayor abstracci\u00f3n a la hora de determinar las funcionalidades delegadas en el software y aquellas derivadas al hardware de un sistema particular.<\/p>\n\t\t

Las modernas tecnolog\u00edas de dispositivos l\u00f3gicos configurables (FPGA) permiten aplicar t\u00e9cnicas de dise\u00f1o flexibles que admiten re-dise\u00f1os de hardware no disruptivos del proceso, admitiendo migraciones de funciones del software al hardware y viceversa, optimizando adem\u00e1s aspectos no funcionales como por ejemplo, el consumo de energ\u00eda.<\/p>\n

Esta migraci\u00f3n flexible entre la implementaci\u00f3n de funciones del software y el hardware ha dado lugar a las actuales t\u00e9cnicas de dise\u00f1o concurrente HW\/SW y son el motivador del objetivo propuesto.<\/p>\n

El objetivo del presente proyecto es el desarrollo de metodolog\u00edas basadas en la utilizaci\u00f3n de t\u00e9cnicas de descripci\u00f3n de hardware, dispositivos l\u00f3gicos configurables, soft-processors y t\u00e9cnicas de s\u00edntesis de alto nivel (HLS) para la especificaci\u00f3n y dise\u00f1o de arquitecturas adaptables a los requerimientos temporales de diferentes aplicaciones cr\u00edticas y d\u00e9bilmente cr\u00edticas, conservando la versatilidad de uso de las arquitecturas de prop\u00f3sito m\u00e1s general.<\/p>\n

Estas metodolog\u00edas tendr\u00e1n en cuenta patrones de especificaci\u00f3n para el dise\u00f1o y verificaci\u00f3n de arquitecturas que, orientadas a dispositivos FPGA, presentan componentes de hardware y software fuertemente vinculados. Este objetivo est\u00e1 en concordancia con las actividades de investigaci\u00f3n y desarrollo realizada en el PID anterior y se puede considerar como su natural continuaci\u00f3n.<\/p>\n \n \n

<\/div>\n <\/div>\n
\n
\n

Integrantes del Grupo<\/h4>\n

<\/i><\/span> Director<\/p>\n

    \n
  • CAYSSIALS<\/span>, Ricardo Luis <\/span><\/li>\n <\/ul>\n

    <\/i><\/span> Codirector<\/p>\n

      \n
    • De Pasquale<\/span>, Lorenzo <\/span><\/li>\n <\/ul>\n

      <\/i><\/span> Investigador Tesista\t<\/p>\n

        \n \t
      • Laiuppa<\/span>, Adri\u00e1n Hector <\/span><\/li> \n
      • Amado<\/span>, Marth Hugo <\/span><\/li>\n
      • Mosquera<\/span>, Jos\u00e9 Carlos <\/span><\/li>\n
      • Banfi <\/span>, Damian <\/span><\/li> \n <\/ul>\n

        <\/i><\/span> Investigador Formado<\/p> \n

          \n
        • IPARRAGUIRRE<\/span>, Javier <\/span><\/li>\n <\/ul>\n

          <\/i><\/span> Becario Doctoral<\/p> \n

            \n
          • TRAPAGLIA MANSILLA<\/span>, Mat\u00edas Daniel <\/span><\/li>\n <\/ul>\n

            <\/i><\/span> Becario BINID<\/p> \n

              \n
            • Vel\u00e1squez<\/span>, Gabriela <\/span><\/li>\n <\/ul>\n
              <\/div>\n <\/div>\n <\/div> \n<\/div>\n","protected":false},"excerpt":{"rendered":"

              4461TC M\u00e9todos concurrentes para Arquitecturas Digitales en Dispositivos L\u00f3gicos Configurables (FPGA). Director: Cayssials, Ricardo Lu\u00eds Inicio: 01\/01\/2017 Finalizaci\u00f3n: 31\/12\/2019<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"disabled","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"footnotes":""},"categories":[117],"tags":[114],"class_list":["post-1584","post","type-post","status-publish","format-standard","hentry","category-finalizados-con-incentivo","tag-sitic"],"_links":{"self":[{"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/posts\/1584"}],"collection":[{"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/comments?post=1584"}],"version-history":[{"count":0,"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/posts\/1584\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/media?parent=1584"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/categories?post=1584"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.frbb.utn.edu.ar\/frbb\/wp-json\/wp\/v2\/tags?post=1584"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}